1. Field of the Invention
The present invention relates to a method capable of reducing DC (direct-current) current operating in the standby mode of a low power dynamic random access memory (DRAM), and more particularly, to a method capable of effectively reducing the DC current induced by gate induced drain leakage (GIDL) effect.
2. Description of the Prior Art
In the recent years, portable devices, like cellular phone, PDA, notebook computers, are getting popular in our everyday life and the power saving requirement has become one of the main design objectives for those electronic products. Numerous efforts have been spent by circuit designers and engineers for reducing the power consumption of the electronic devices.
One of the primary items for low power DRAM design is to reduce DC current in a standby mode to meet the requirements of “Idd6” specifications, proposed by JEDEC, the Joint Electronic Device Engineering Council. The Idd6 specification for standby mode is important because it is closely related to the length of time for the electronic device to stay in the standby mode. If the standby time of the electronic device can be extended, the user convenience can be improved, and the portability of the device can also be advanced.
Please refer to FIG. 1, which illustrates a schematic diagram of a wordline driver 10. The wordline driver 10 is a hierarchical wordline architecture, and can be divided into a double layered structure comprising a main wordline driver 100, a local wordline driver 102 and a voltage supply 104. The major function of the voltage supply 104, usually a charge pump circuit, is to provide an output voltage VPP at about 2.6 volt and the one lower than the ground voltage GND at −0.6 volt, which are responsible for both the operations of the main wordline driver 100 and the local wordline driver 102. The charge pump circuit is a very useful circuit but is also known for poor power efficiency, and it could magnify an internal leakage current to a larger external current.
The main wordline driver 100 comprises circuits for row address decoding and level shifting, where a p-type MOS transistor MP1 and an n-type MOS transistor MN1 are utilized for driving the local wordline driver 102. And, in the local wordline driver 102, a p-type MOS transistor MP2 and an n-type MOS transistor MN2 are utilized for driving the local wordline used for a memory access. In the wordline driver 10, a local wordline voltage VLWL is selected HIGH at VPP only when both a wordline driving voltage VWLDV is selected HIGH at VPP, and an inverted main wordline voltage VBMWL is output LOW at VNWL. To further demonstrate the operations of the local wordline driver 102, please refer to FIG. 2, which illustrates a table 20 indicating signal levels related to the local wordline driver 102. In FIG. 2, the last row of the table 20 indicates the output voltage level of VLWL by varying the input voltage levels of VBMWL and VWLDV, and the last column indicated the standby condition.
In the wordline driver 10, the n-type MOS transistor MN1 in the main wordline driver 100 exhibits a leakage current owing to the gate induced drain leakage (GIDL) effect. This effect is introduced by the high gate to drain and high drain to bulk voltage when the n-type MOS MN1 is in an OFF condition. Inside the n-type MOSFET MN1, where the gate voltage is lower than the drain voltage, there is a narrow depletion width located at the gate-to-drain overlap region. The strong electric field induced by the voltage drop between gate and drain makes the electrons tunnel from the valence band to conduction band and become free electrons. The free electrons generated by this effect will move to drain as leakage current. The GIDL effect is more easily observed when the drain to bulk voltage difference of the n-type MOS MN1 gets larger. Eventually, this unfavorable GIDL current is magnified by the inefficiency of the charge pump circuit and adds to the total current output from the external power source. When this happened, it is more likely the Idd6 requirement would be violated. The specification for a low power DRAM device becomes difficult to be realized.